1. Technical Field
The present invention relates to stacked layer type semiconductor devices, and more particularly, to a stacked layer type semiconductor device having an increased processing speed, and a semiconductor system including the stacked layer type semiconductor device.
2. Description of Related Art
Semiconductor integrated circuits, for example, memory packaging technology, have been continuously developed to satisfy needs for memory miniaturization and packing efficiency. With the need for miniaturization and high performance of electric/electronic products, various techniques of stacking memories are being developed. The memory stacking denotes a technique of stacking at least two memories, one over another. The stacked memories may realize products with memory capacities twice as great as those of single-layered memories, and increase the geometric efficiency of an area on which memories are mounted.
In a conventional stacked memory, a plurality of memories are stacked on a circuit board by using an adhesion means such as adhesive, and each of the memories are electrically connected to the circuit board via a connection means such as a wire. The stacked memories and the circuit board may be packaged by a sealant such as Epoxy Molding Compound (EMC). Solder balls or connection pins that allow a package, namely, a circuit board, to be connected to an external circuit may be attached to a lower portion of the package, namely, the circuit board.
However, the memories of the convention stacked memory are connected to one another via wires. This structure may decrease the signal processing speed of stacked memory. In addition, since an additional area for wire bonding is required, the size of stacked memory increases.